Switched ADC BMS

[johu]

Pretty cool idea. Since balancing only makes sense when there is no current flow there is also no risk of missing an over voltage event.

[johu]

Now after running 6 modules in my ESS for some weeks with old, high R_int LFP batteries there are some observations:

- it is dead stable, even over multiple power cycles and even with some 2.1 modules in there
- SoC calculation is all over the place. Sometimes it estimates when there's still current flowing
- SoH calculation is completely off
- Charge curve parameters need to be tuned carefully to avoid oscillation. Will attach my configuration later
- It would be good to have hysteresis. So when ucellmax is reached it should output 0 charge setpoint until ucellmax-threshold is reached
- internal resistance estimation could come in useful

[johu]

Will try playing with those resistors the next time I open the bike up, thank you for the advice!

Just found there is a software way to do it. Right now the lower two FETs are closed for dissipative balancing. That is via the 2x10R resistors. If the upper two FETs are closed it would skip those resistors.

[skr]

Just this morning my sleep deprived brain was wondering about this by trying to visualize the current flow.

First need to get rid of PTCs in front of my cell taps, as most likely they shoot up in resistance at summer temps just above 100mA.

Given the low duty cycle imo targeting a few hundred mA balancing on 750mA MEB fuse should be safe. Maybe PWM them between open and closed for variable current flow.

Let me know if you figure out the logic for fets, I am a bit skeptical on experimenting this not on my no longer existing bench setup and not sure when I can find a moment to make a new setup.

[skr]

Johu- would you be interested in continuing this design in a direction which branches off from the one set out originally, most importantly - "no big balancing resistors"?

I envision basically the same design, but extra cell tap and i2c headers for a sub board made out of single sided aluminum core with power fets and parallel balance resistors, same opto gate layout and i2c io expander to connect each cell to balancing resistors, maybe some thermal monitoring to throttle as needed.
That way bms could be same as now or top bleeding heater if one chooses so. Gives more utility for more broader set of scenarios imo.

Another big one could be iso can and power for the board from outer cell taps, so the thing can run autonomously in the background with or without 12v supplied.

The first one would be pretty easy to implement imo, second one mavbe is of little significance in ev swaps, but my motorcycle with no constant 12v source would love it.

I can kicad all of it, have no business interests, but would love to hear your thoughts if this would be interesting for you. Timeline wise - I could throw hours at it most likely this winter.

[EdAtki]

I'm thinking of reusing a lot of this code for my MAX17823 BMS, for those unaware this would be a master BMS that talks to the built in satellite BMS in OEM modules from Kia, Peugeot, Citroen, Opel and potentially others. In fact I'm wondering what people's opinions are on adding support for different hardware to the existing firmware rather than create a separate project. I'd keep the same processor and pinout as much as possible so the changes would mainly be confined to replacing the FlyingAdcBms class initially (although this would be mimicking the behaviour and limitations of only being able to measure or balance one cell at a time despite that no longer being the case, so some additional future work to get the full potential).

[johu]

I could shell out some modules to libopeninv?

[EdAtki]

Potentially, most of the modules are quite specific to BMS applications though so I think leaving them part of the firmware is fine.

I just envisage a common open source firmware for a variety of BMS boards. In much the same way open inverter supports a variety of inverters.