mainboardV3 version output driver differences ?

[Bratitude]

i noticed when looking at the output driver schematic on git hub and the schematic on the wiki, they are in fact different.

wiki version has:
2 driver lines paralleled for out_dcsw
1 driver line for out_pre

github version:
2 driver lines paralleled for out_pre
1 line driving a N-chanel fet (ap9t18gh) for out_dcsw

according to the uln2003 data sheet https://www.ti.com/lit/ds/symlink/uln20 ... e.com%252F "The collector-current rating of a single Darlington pair is 500 mA"

so the github version should handle directly driving a contractor drawing .36amps on ether the out_dcsw or out_pre ?

wiki:

github:

i'll update the wiki once this is cleared up

[johu]

Yes, indeed, never updated that.
The little 16-SOIC only handles small relays, so I thought beefing this up might make sense.

[Bratitude]

Yes, indeed, never updated that.
The little 16-SOIC only handles small relays, so I thought beefing this up might make sense.

Awesome!

Just for clarity, how much can out_dcsw and out_pre sink?

[johu]

Awesome!

Just for clarity, how much can out_dcsw and out_pre sink?

I'd say like 500 mA for precharge. DC switch I cannot say. The FET is only driven with 3.3V so not as low Rds as can be. I guess 2-3A should be doable without anything overheating.

[Bratitude]

I'd say like 500 mA for precharge. DC switch I cannot say. The FET is only driven with 3.3V so not as low Rds as can be. I guess 2-3A should be doable without anything overheating.

thanks!
updated the wiki