Switched ADC BMS

[johu]

Starting tests with real cells now, courtesy of pm_dawn in Östersund. He borrowed a scooter battery to me which, conveniently is unbalanced and one module is even below 2V. So now I can do some testing of the balancing

Accuracy looks very good. Calibrated one channel to the multimeter reading and all others match that as well. You can see a small 0.5mV jitter when voltage is between two digits. Otherwise it is rock stable.

The sinusoidal form comes from the power supply during charging.

[johu]

Left it running all night in balancing mode. So it measures cell voltage in one cycle, then if it's below average it diverts current from the DC/DC converter otherwise it bleeds current.

As you can see it has brought down the delta from 16.5 mV to 13 mV but bumping up low cells didn't really happen.

It does make the effort as you can see on cursor 1 and 2 where it brings the voltage up from 3548 to 3570 mV (22 mV delta). In contrast dissipative balancing bring the voltage down from 3585 to 3.515 mV (70 mV delta). Keep in mind this is behind the multiplexer so a lot of that will be mosfet turn on resistance.

Right now balancing resistors are 2x47R, I will bring them down to 2x22 on the next rev for bleeding and 1x22 for bumping up. I could also try shorting one or both, what could possibly go wrong

[arber333]

Starting tests with real cells now, courtesy of pm_dawn in Östersund. He borrowed a scooter battery to me which, conveniently is unbalanced and one module is even below 2V. So now I can do some testing of the balancing

Accuracy looks very good. Calibrated one channel to the multimeter reading and all others match that as well. You can see a small 0.5mV jitter when voltage is between two digits. Otherwise it is rock stable.

The sinusoidal form comes from the power supply during charging.

Nicely thought out.
May i suggest a more linear setup . I use 12S battery and i added my variable PSU in series with last positive cell in such a way i have control over last voltage. BMS thinks it sees the 13th cell and i can test various effects of its voltage change.
Additional benifit would also be the PSU can show current flowing and this shows effect of BMS balancing. Of course i use 5A fuse inline just in case.

[johu]

Good news: I have reduced the total balancing resistance to 22 Ohms and that makes balancing more effective. Can bump up cells with 60 mA now and discharge with... well would have to do the arber method (actually have done so before to measure bleed off current)

More good news: I have tested with all 16 channels and it works a treat

Bad news: One module, like said was sitting very low and I bumped it up with my lab supply. I was wiggling the banana plugs a bit and suddenly the Analog Discovery was on fire (what's that, the 5th?) and my laptop shut off. Aftermath: laptop right hand side USB connectors dead but laptop alive. Analog Discovery: dead. BMS board: Alive

Cause: the negative cable inside the power supply had wiggled loose and made contact with PE. Laptop is also on PE, Analog Discovery on PE and said negative cable was on cell 16 or about 60V and now suddenly on PE.

I have a spare right hand side sub board for the laptop back in Germany (hmm, how come?) so that's an easy fix. The AD will set me back 375€ at digikey. The inevitable cost of HW development...

[arber333]

Ugh... tough.

I recently burned up two of those JK BMS modules. I found out that despite them being rated for 24S the pack voltage at 4V * 24S can jump across the small mosfet gap and toast the last two 100V fets!

I hope i solved this by derating myself to 16S per module from now on...

Despite this i am very carefull with my test setup...

[bexander]

Good news: I have reduced the total balancing resistance to 22 Ohms and that makes balancing more effective. Can bump up cells with 60 mA now and discharge with... well would have to do the arber method (actually have done so before to measure bleed off current)

Would it be possible to measure the voltage across the load resistor while balancing? If so, you can calculate the current as the resistance is known.

[johu]

You mean during operation or right now with a multimeter?

In operation is difficult as the secondary side ADC has only one channel

JK BMS is funky with these enormous caps for balancing!

[bexander]

I ment during operation, with a multimeter or oscilloscope, to get a good estimate of the current.

[johu]

New revision, more mistakes made

The most annoying one: I specified the wrong part number for all 10k resistors and now they are all 1 Ohm! Quite a few of them used. With that fixed everything powers up but the mux has glitchs. My little reset circuitry needs adjustment. With that fixed the mux works as before. I2C comms also works.
I think I should break out a the serial port to get the console back, doing it all via CAN is clumsy right now. But maybe it speeds up CAN development, most of all the boot loader.

Will now change all the pull-up resistors in the mux and then connect the battery back up.

[johu]

Functionality restored:

[johu]

Hooked up Dave tool:

Code: Select all

uavg                :       4052 [mV]
umin                :    4041.16 [mV]
umax                :    4097.31 [mV]
udelta              :    56.1562 [mV]
u0                  :    4048.19 [mV]
u1                  :    4051.09 [mV]
u2                  :    4052.88 [mV]
u3                  :    4051.09 [mV]
u4                  :    4045.84 [mV]
u5                  :     4043.5 [mV]
u6                  :    4042.34 [mV]
u7                  :    4045.25 [mV]
u8                  :    4052.88 [mV]
u9                  :    4045.25 [mV]
u10                 :    4048.19 [mV]
u11                 :    4058.12 [mV]
u12                 :    4097.31 [mV]
u13                 :    4048.19 [mV]
u14                 :    4041.16 [mV]
u15                 :    4062.81 [mV]

Currently doing a balance run to see how the delta develops.

Found a hardware issue: if you falsely connect two or more cells across one channel the excess voltage will conduct through the limiting resistors and diodes of the balancing bridge into the poor components of the 5V rail, destroying them. As long as the mux doesn't switch you can hook up anything you want (below the FET breakdown voltage).
So a) I need a TVS across the 5V rail and b) the software needs to check for excess voltage in the fastest ADC mode where it only briefly connects all channels to the mux

Source code is here: https://github.com/jsphuebner/FlyingAdcBms
Needs a little tweak in stm32_can

Code: Select all

{ CAN_BTR_TS1_13TQ, CAN_BTR_TS2_2TQ, 3 }, //500kbps

The CAN timing is clock dependent, need to find an automated way to handle that. BMS will run only at 24 MHz.

[johu]

Result after about 18 hours of balancing:

Code: Select all

uavg                :    4051.69 [mV]
umin                :     4043.5 [mV]
umax                :    4091.47 [mV]
udelta              :    47.9688 [mV]
utotal              :    64827.3 [mV]
u0                  :    4048.78 [mV]
u1                  :    4050.53 [mV]
u2                  :    4051.09 [mV]
u3                  :    4051.09 [mV]
u4                  :       4047 [mV]
u5                  :    4044.69 [mV]
u6                  :     4043.5 [mV]
u7                  :    4046.44 [mV]
u8                  :    4051.09 [mV]
u9                  :       4047 [mV]
u10                 :    4049.94 [mV]
u11                 :    4052.88 [mV]
u12                 :    4091.47 [mV]
u13                 :    4050.53 [mV]
u14                 :    4044.09 [mV]
u15                 :    4057.53 [mV]

Delta dropped from 56 to 48 mV, lowest cell taken from 4041 to 4043 mV and highest cell taken from 4097 to 4091 mV

[johu]

And after 30 hours

Code: Select all

uavg                :    4051.19 [mV]
umin                :    4044.69 [mV]
umax                :    4086.78 [mV]
udelta              :    42.0938 [mV]
utotal              :    64819.2 [mV]
u0                  :    4048.78 [mV]
u1                  :    4049.94 [mV]
u2                  :    4049.94 [mV]
u3                  :    4049.94 [mV]
u4                  :    4047.59 [mV]
u5                  :    4045.25 [mV]
u6                  :    4044.09 [mV]
u7                  :       4047 [mV]
u8                  :    4050.53 [mV]
u9                  :    4048.19 [mV]
u10                 :    4049.94 [mV]
u11                 :    4051.69 [mV]
u12                 :    4086.78 [mV]
u13                 :    4050.53 [mV]
u14                 :    4045.84 [mV]
u15                 :    4052.88 [mV]

Down to 42 mV delta from 56. So 24 mV 14 mV in 30 h makes it 0.5 mV/h on my test battery of 26 Ah. My clamp meter isn't quite the best equipment for this kind of current, it measures 30 mA of charging and 50 mA of discharging. My bench supply shows a power delta of 300 mW during charging which would point to 75 mA, maybe 50 mA counting 30% losses.
So yes that's slow and would be even slower on a larger pack. But it is facing a quite unbalanced pack and I think the balancing capability should be sufficient for a pack under continuous treatment.

[johu]

43 hours into the experiment:

Code: Select all

uavg                :    4051.47 [mV]
umin                :    4045.84 [mV]
umax                :    4081.53 [mV]
udelta              :    35.6562 [mV]
utotal              :    64823.8 [mV]
u0                  :    4049.34 [mV]
u1                  :    4049.94 [mV]
u2                  :    4050.53 [mV]
u3                  :    4049.94 [mV]
u4                  :    4048.19 [mV]
u5                  :    4046.44 [mV]
u6                  :    4045.84 [mV]
u7                  :    4048.78 [mV]
u8                  :    4050.53 [mV]
u9                  :    4049.34 [mV]
u10                 :    4050.53 [mV]
u11                 :    4051.09 [mV]
u12                 :    4081.53 [mV]
u13                 :    4050.53 [mV]
u14                 :    4048.19 [mV]
u15                 :    4052.28 [mV]

Down to about 35 mV, still 0.5 mV/h (corrected in post above)

Having some new ideas about input protection. So TVS for limiting voltage on the ADC power rail to about 6V and then a TL431 reference triggering at around 5.5V via the remaining free channel of the digital isolator. That then triggers a pin change interrupt which turns off the multiplexer and signals an error. Turning off the multiplexer takes around 100 us, I hope the TVS and transistors will hold up that long. The maximum voltage supported is about 70V, if that rushes in via the 22 Ohm limiting resistor + FET losses we are looking at 3A for 100 us. Anyone savvy enough to calculate heat dissipation?

Also thinking about supplying the mux control with a high voltage linear reg, would result in a continuous draw of about 1 mA from the cells. Maybe not the greatest idea but deploying a 200 mA DC/DC converter for delivering 1 mA seems wasteful as well.

[bexander]

Also thinking about supplying the mux control with a high voltage linear reg, would result in a continuous draw of about 1 mA from the cells. Maybe not the greatest idea but deploying a 200 mA DC/DC converter for delivering 1 mA seems wasteful as well.

What are you trying to achive? A isolated DC supply of 1mA to the MUX? Maybe a swiched capacitor topology or similar could work?

[Pete9008]

Anyone savvy enough to calculate heat dissipation?

Sorry no, too many variables/unknowns for any calculation to be of much value here. Best option is to see if the FET's and resistors (or equivalents) give any pulse ratings for current or power.

[johu]

What are you trying to achive? A isolated DC supply of 1mA to the MUX? Maybe a swiched capacitor topology or similar could work?

Yes, this part of the circuit:

Some 74 series gates and an isolator. Haven't measured current draw when it's switching, only quiescent.

There are 3 potential groups: LV, HV_mux, HV_adc. HV_adc is the one that's floating to the channel currently switched in and whos DC/DC is also used for bumping up low cells. HV_mux is at a fixed HV potential and HV_adc can be within 0-70V of it. Are you thinking it is possible to supply the mux from HV_adc?

Sorry no, too many variables/unknowns for any calculation to be of much value here. Best option is to see if the FET's and resistors (or equivalents) give any pulse ratings for current or power.

Either that or I test with some older revision boards

[bexander]

Maybe, something in that way. Supply power from somewhere that is not battery powered.
I relized that switched capacitor won't work, they don't provide isolation.
Switch mode isolated DC/DC other then beeing expensive is that they tend to burn a lot of quiescient current, like 20mA or so. So not a good option in this case.

Would it be possible to let the TL431 directly turn of the power, via a p-fet or pnp transistor, to speed up turn-off

[johu]

Almost done after 65 h

Code: Select all

uavg                :    4050.22 [mV]
umin                :    4048.19 [mV]
umax                :    4060.47 [mV]
udelta              :    12.2812 [mV]
utotal              :    64803.9 [mV]
u0                  :    4048.78 [mV]
u1                  :    4049.34 [mV]
u2                  :    4049.34 [mV]
u3                  :    4049.34 [mV]
u4                  :    4048.19 [mV]
u5                  :    4048.19 [mV]
u6                  :    4048.19 [mV]
u7                  :    4048.78 [mV]
u8                  :    4050.53 [mV]
u9                  :    4049.94 [mV]
u10                 :    4050.53 [mV]
u11                 :    4050.53 [mV]
u12                 :    4060.47 [mV]
u13                 :    4051.09 [mV]
u14                 :    4049.34 [mV]
u15                 :    4051.09 [mV]

I changed the code to stop charging cells that are within 3 mV of the average. That sped up the balancing process significantly because more time could be spent on u12. So we have lowered delta from 56 to 12 mV in 65 hours, 0.7 mV/h.

Maybe, something in that way. Supply power from somewhere that is not battery powered.
I relized that switched capacitor won't work, they don't provide isolation.
Switch mode isolated DC/DC other then beeing expensive is that they tend to burn a lot of quiescient current, like 20mA or so. So not a good option in this case.

Yes considering the fact that it will be running for many hours with the car off, standby losses should be decreased as much as possible. Right now it draws 20 mA from 12V while not active balancing. 6 modules would thus draw 120 mA.
The problem can be split into two parts: 1st: how do we initially power up the mux? 2nd: how do we keep it powered once in operation?

Would it be possible to let the TL431 directly turn of the power, via a p-fet or pnp transistor, to speed up turn-off

Many things can be done if necessary. Will see how much I can go up with mux clock speed first.
EDIT: also the signal needs to latch, otherwise after turning off and will turn right on again because the fault condition is gone.

[johu]

And after 72h we're done, down to 3mV delta.

Code: Select all

uavg                :    4048.41 [mV]
umin                :    4046.44 [mV]
umax                :    4049.94 [mV]
udelta              :        3.5 [mV]
utotal              :    64774.7 [mV]
u0                  :       4047 [mV]
u1                  :    4048.19 [mV]
u2                  :    4048.19 [mV]
u3                  :    4048.19 [mV]
u4                  :       4047 [mV]
u5                  :    4046.44 [mV]
u6                  :    4046.44 [mV]
u7                  :    4047.59 [mV]
u8                  :    4049.34 [mV]
u9                  :    4048.78 [mV]
u10                 :    4049.34 [mV]
u11                 :    4049.34 [mV]
u12                 :    4049.94 [mV]
u13                 :    4049.34 [mV]
u14                 :    4049.34 [mV]
u15                 :    4049.34 [mV]

So over all 0.7 mV/h now. I think there is still some optimization possible with the resistors, e.g. 10 instead of 22 Ohm. Bleeding runs through two of them, 44 Ohm, charging runs through just one.

[johu]

To round off the little science project, here's some diagrams.
Individual cell voltages:

Obviously one was way out, the others already close

The essence of that:

Lowest cell started out at 4041 mV, highest at 4097 mV. Final average cell voltage is 4049 mV. So instead of dissipating 15 cells down to 4041 mV we just needed to dissipate 7 cells down to 4049 mV while the others were taken up to 4049 mV. Also we see the balance target drop from 4051 mV to 4049 mV because we took the highest cell down quite far. That why towards the end the min voltage drops again. The strategy of first taking high cells down to the average, then bumping low cells up would prevent that.

[johu]

This would be a variant of mux power supply that is only active when the BMS is powered:

The Zener regulates voltage to something around 5V. The base pull-up serves as an enable input and would be connected to the ADCs power supply through a high value resistor. So even when it swings to the highest cell at 70V the current through the resistor is very small (0.7 mA). The 16S battery would be loaded with the actual logic draw + said 0.7mA but only in active operation.

When the BMS is off there is still no current draw from the cells what so ever.

What troubles me is that a variable current flows through the mux now, the higher potential the selected the cell, the more current. That could disturb the ADC reading, so a higher cell reads lower voltage then a lower one.

[bexander]

The Zener regulates voltage to something around 5V. The base pull-up serves as an enable input and would be connected to the ADCs power supply through a high value resistor. So even when it swings to the highest cell at 70V the current through the resistor is very small (0.7 mA). The 16S battery would be loaded with the actual logic draw + said 0.7mA but only in active operation.

When the BMS is off there is still no current draw from the cells what so ever.

What troubles me is that a variable current flows through the mux now, the higher potential the selected the cell, the more current. That could disturb the ADC reading, so a higher cell reads lower voltage then a lower one.

Note that with your circuit above you will have a power loss of 65mW/1mA of current consumed in Q1, assuming 70V input power.
The zener diode have no bias current, hence your low output voltage compared to your choise of 6,2V zener. This risks a large variation of output voltage for small variation in temperature and/or R2 current.

I still don't understand fully what you are trying to do as I can't find a complete schematic of your circuit, including the power supplies? Can you post or send me the complete schematic? KiCad or pdf. Then maybe I can be more helpful.

[johu]

Discussed with bexander that the robustness against 70V is quite tough. He further suggests placing the TVS before the transistor bridge but even then the SMD resistors will briefly need to dissipate 95W each or 190W with the TVS across VDDA. We don't think they'll survive that for any amount of time.

Another possibility would be to have a bidirectional TVS right across the mux output and adding a fuse.

Had an idea to immensely shorten the time they are exposed to the fault current: the mux is clocked with 100 kHz, so it takes 40 us to turn it from off to on. So with a 16 bit control word it is possible to select a channel and then 40us later turn the mux is off again. Afterwards the ADC can measure the voltage that has built up in the smoothing capacitor C7 and from it decide whether the channel is connected to a voltage in range.

Did a simulation. With 4.2V, the highest valid reading, we get an average value of 89 mV. I think Sigma/Delta ADCs do average the input over sampling time (4 ms), right?
With an input voltage of 7V we get an average of 105 mV. And at 16V 84 mV. Oh! It seems as soon as the TVS steps into action the average is lower. So that's not good then.

[celeron55]

I like simple but overkill solutions. If you need to protect something from overvoltage, a TVS and a PPTC fuse is very effective, as long as you're aware of and ok with the capacitance and leakage current of the TVS and the current vs. time behavior of the PPTC fuse.